? semiconductor components industries, llc, 2010 october, 2010 -- rev. 9 1 publication order number: nb2304a/d nb2304a 3.3 v zero delay clock buffer the nb2304a is a versatile, 3.3 v zero delay buffer designed to distribute high--speed clocks in pc, workstation, datacom, telecom and other high--performance applications. it is available in an 8 pin package. the part has an on--chip pll which locks to an input clock presented on the ref pin. the pll feedback is required to be driven to fbk pin, and can be obtained from one of the outputs. the input--to--output propagation delay is guaranteed to be less than 250 ps, and the output--to--output skew is guaranteed to be less than 200 ps. the nb2304a has two banks of two outputs each. multiple nb2304a devices can accept the same input clock and distribute it. in this case, the skew between the outputs of the two devices is guaranteed to be less than 500 ps. the nb2304a is available in two different configurations (refer to nb2304a configurations table). the nb2304ai1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. the nb2304ai1h is the high--drive version of the --1 and the rise and fall times on this device are much faster. the nb2304ai2 allows the user to obtain ref, 1/2 x and 2x frequencies on each output bank. the exact configuration and output frequencies depend on which output drives the feedback pin. features ? zero input -- output propagation delay, adjustable by capacitive load on fbk input ? multiple configurations -- refer t o nb2304a configurations table ? input frequency range: 15 mhz to 133 mhz ? multiple low--skew outputs ? output--output skew < 200 ps ? device--device skew < 500 ps ? two banks of four outputs ? less than 200 ps cycle--to--cycle jitter (--1, --1h, --5h) ? available in space saving, 8 pin 150 mil soic package ? 3.3 v operation ? advanced 0.35 m cmos technology ? guaranteed across commercial and industrial temperature ranges ? these are pb--free devices marking diagram* xxxx = device code a = assembly location l = wafer lot y = year w = work week g = pb--free package *for additional marking information, refer to application note and8002/d. soic--8 d suffix case 751 see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information http://onsemi.com 1 8 xxxx alyw g 1 8
nb2304a http://onsemi.com 2 figure 1. basic block diagram (see figures 11 and 12 for device specific block diagrams) fbk clka1 clka2 clkb1 clkb2 ref pll extra divider (--2) 2 table 1. configurations device feedback from bank a frequency bank b frequency nb2304ai1 bank a or bank b reference reference nb2304ai1h bank a or bank b reference reference nb2304ai2 bank a reference reference 2 nb2304ai2 bank b 2 x reference reference figure 2. pin configuration v dd 1 2 3 4 8 7 6 5 ref clka1 clka2 gnd fbk clkb2 clkb1 nb2304a table 2. pin description pin # pin name description 1 ref (note 1) input reference frequency, 5 v tolerant input. 2 clka1 (note 2) buffered clock output, bank a. 3 clka2 (note 2) buffered clock output, bank a. 4 gnd ground. 5 clkb1 (note 2) buffered clock output, bank b. 6 clkb2 (note 2) buffered clock output, bank b. 7 v dd 3.3 v supply. 8 fbk pll feedback input. 1. weak pulldown. 2. weak pulldown on all outputs.
nb2304a http://onsemi.com 3 table 3. maximum ratings parameter min max unit supply voltage to ground potential -- 0 . 5 +7.0 v dc input voltage (except ref) -- 0 . 5 v dd +0.5 v dc input voltage (ref) -- 0 . 5 7 v storage temperature -- 6 5 +150 ? c maximum soldering temperature (10 sec) 260 ? c junction temperature 150 ? c static discharge voltage (per mil--std--883, method 3015) > 2000 v stresses exceeding maximum ratings may dam age the device. maximum ratings are stres s ratings only. functional operation above the recommended operating conditions is not impli ed. extended exposure to stresses above the re commended operating conditions may affect device reliability. table 4. operating conditions parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) industrial commercial -- 4 0 0 85 70 ? c c l load capacitance, 15 mhz to 100 mhz 30 pf c l load capacitance, from 100 mhz to 133 mhz 15 pf c in input capacitance (note 3) 7 pf 3. applies to both ref clock and fbk. table 5. electrical characteristics v cc = 3.0 v to 3.6 v, gnd = 0 v, t a =--40 ? cto+85 ? c parameter description test conditions min max unit v il input low voltage 0.8 v v ih input high voltage 2.0 v i il input low current v in =0v 50.0 m a i ih input high current v in =v dd 100.0 m a v ol output low voltage i ol = 8 ma (--1, --2) i ol =12ma(--1h) 0.4 v v oh output high voltage i oh = --8 ma (--1, --2) i oh =--12ma(--1h) 2.4 v i dd supply current unloaded outputs 100 mhz ref select inputs at v dd or gnd 45 ma unloaded outputs, 66 mhz ref (--1, --2) 35 unloaded outputs, 33 mhz ref (--1, --2) 20
nb2304a http://onsemi.com 4 table 6. switching characteristics v cc = 3.0 v to 3.6 v, gnd = 0 v, t a =--40 ? cto+85 ? c (all parameters are specified with loaded outputs) parameter description test conditions min typ max u nit t 1 output frequency 30 pf load (all devices) 15 pf load (--1, --2) 15 15 100 133.3 mhz t 1 duty cycle = (t 2 /t 1 ) * 100 (all devices) measured at 1.4 v, f out 66.66 mhz 30 pf load 40.0 50.0 60.0 % measured at 1.4 v, f out 50 mhz 15 pf load 45.0 50.0 55.0 t 3 output rise time (--1, --2) measured between 0.8 v and 2.0 v 30 pf load 2.50 ns measured between 0.8 v and 2.0 v 15 pf load 1.50 output rise time (--1h) measured between 0.8 v and 2.0 v 30 pf load 1.50 t 4 output fall time (--1, --2) measured between 2.0 v and 0.8 v 30 pf load 2.50 ns measured between 2.0 v and 0.8 v 15 pf load 1.50 output fall time (--1h) measured between 2.0 v and 0.8 v 30 pf load 1.25 t 5 output--to--output skew on same bank (--1, --2) all outputs equally loaded 200 ps output--to--output skew (--1h) all outputs equally loaded 200 output bank a--to--output bank b skew (--1) all outputs equally loaded 200 output bank a--to--output bank b skew (--2) all outputs equally loaded 400 t 6 delay, ref rising edge to fbk rising edge measured at v dd /2 0 ? 250 ps t 7 device--to--device skew measured at v dd /2 on the fbk pins of the device 0 500 ps t 8 output slew rate measured between 0.8 v and 2.0 v using te s t c i r c u i t # 2 1 v/ns t j cycle--to--cycle jitter (--1, --1h) measured at 66.67 mhz, loaded outputs, 15 pf load 180 ps measured at 66.67 mhz, loaded outputs, 30 pf load 200 measured at 133.3 mhz, loaded outputs, 15 pf load 100 cycle--to--cycle jitter (--2) measured at 66.67 mhz, loaded outputs, 30 pf load 400 ps measured at 66.67 mhz, loaded outputs, 15 pf load 380 t lock pll lock time stable power supply, valid clock presented on ref and fbk pins 1.0 ms
nb2304a http://onsemi.com 5 zero delay and skew control for applications requiring zero input--output delay, all outputs must be equally loaded. figure 3. ref input to clka/clkb delay vs. difference in loading between fbk pin and clka/clkb pins 1500 1000 500 0 --500 --1000 --1500 -- 3 0 -- 2 5 -- 2 0 -- 1 5 -- 1 0 -- 5 0 5 1 0 1 5 2 0 2 5 3 0 ref input to clka/clkb dela y (ps) output load difference: fbk load -- clka/clkb load (pf) to close the feedback loop of the nb2304a, the fbk pin can be driven from any of the four available output pins. the output driving the fbk pin will be driving a total load of 7 pf plus any additional load that it drives. the relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. this is shown in figure 3. for applications requiring zero input--output delay, all outputs including the one providing feedback should be equally loaded. if input--output delay adjustments are required, use figure 3 to calculate loading differences between the feedback output and remaining outputs. for zero output--output skew, be sure to load outputs equally. switching waveforms figure 4. duty cycle timing 1.4 v 1.4 v 1.4 v t 1 t 2 figure 5. all outputs rise/fall time t 3 output 2.0 v 0.8 v t 4 2.0 v 0.8 v 3.3 v 0v 1.4 v 1.4 v t 5 figure 6. output -- output skew output output t 6 input output figure 7. input -- output propagation delay v dd 2 v dd 2 figure 8. device -- device skew t 7 fbk_device 1 v dd 2 v dd 2 fbk_device 2
nb2304a http://onsemi.com 6 v dd v dd c load gnd gnd outputs figure 9. test circuit #1 10 pf 0.1 m f 0.1 m f v dd v dd gnd gnd outputs 0.1 m f 0.1 m f 1k 1k figure 10. test circuit #2 for parameter t 8 (output slew rate) on --1h devices v dd test circuits figure 11. nb2304ai1 and nb2304ai1h fbk clka1 clka2 clkb1 clkb2 ref pll figure 12. nb2304ai2 fbk clka1 clka2 clkb1 clkb2 ref pll 2 block diagrams ordering information device marking operating range package shipping ? availability NB2304AI1DG 4i1 industrial & commercial soic--8 (pb--free) 98 units / rail now nb2304ai1dr2g 4i1 industrial & commercial soic--8 (pb--free) 2500 tape & reel now nb2304ai1hdg 4i1h industrial & commercial soic--8 (pb--free) 98 units / rail now nb2304ai1hdr2g 4i1h industrial & commercial soic--8 (pb--free) 2500 tape & reel now nb2304ai2dg 4i2 industrial & commercial soic--8 (pb--free) 98 units / rail now nb2304ai2dr2g 4i2 industrial & commercial soic--8 (pb--free) 2500 tape & reel now ?for information on tape and reel specificat ions, including part orientation and tape si zes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb2304a http://onsemi.com 7 package dimensions soic--8 nb case 751--07 issue aj seating plane 1 4 5 8 n j x45 _ k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751--01 thru 751--06 are obsolete. new standard is 751--07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0808 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 -- x -- -- y -- g m y m 0.25 (0.010) -- z -- y m 0.25 (0.010) z s x s m ____ 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 ? mm inches ? scale 6:1 *for additional information on our pb--free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation speci al, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performa nce may vary over time. all operating parameters, including ?typicals? must be validated for each custo mer application by customer?s techni cal experts. scillc does not conve y any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical impl ant into the body, or other applications intended to support or sustain life, or fo r any other application in which the failure of the scillc product could create a situation wher e personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unaut horized application, buyer shall indemnify and hold scillc and its offic ers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or in directly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such clai m alleges that scillc was negligent regarding the design or manufactur e of the part. scillc is an equal opportunity/affirmative action employer. this literature is subj ect to all applicable c opyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800--282--9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81--3--5773--3850 nb2304a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303--675--2175 or 800--344--3860 toll free usa/canada fax : 303--675--2176 or 800--344--3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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